One or more aspects of the invention relate generally to testing of semiconductor logic chips, and more specifically, to keeping a number of switching transitions of flip-flops during testing below a threshold.
Logic chips have become more and more complex, and the testing of the complex logic has become more and more challenging. Conventionally, logic semiconductor chips have been tested using external automatic test pattern generators (ATPG). However, because of miniaturization and growing complexity it has become more and more challenging to get all signals from an external automatic test pattern generator into the logic circuits on the semiconductor chip, as well as getting all scanned-out data back into the testing system. Thus, logic built-in self-test (LBIST) is an alternative method for testing digital logic on semiconductor chips. Logic built-in self-test is a test method, which allows running the main test loop for chips without any external testers. This test approach typically uses an on-product-block-generator (OPCG) to generate clock sequences for testing, as well as a pseudo random pattern generator (PRPG) and multi-input signal registers (MISR) that are used respectively for pattern generation and response capture. The PRPG generates a test pattern that is supplied into the LBIST scan channels and the response from the scan channels, after the active clock sequence generated by the OPCG, is compressed in MISR(s) which is generally termed as a signature. The LBIST scan channels contain significantly fewer flip-flops than scan chains in a full scan mode. The scanning capture phase generally forms a loop for LBIST which is typically run for many thousands of loops.
During ATPG or LBIST testing, generally more flip-flops will be toggling than in a normal functional mode of the semiconductor chip as the test patterns applied are intended for testing and not for reflecting functional execution. During testing, there are typically about a 50% of 0/1 transitions of flip-flops meaning that there is about 50% switching of flip-flops. On the other side, during functional operation, the generally observed switching rate is much closer to 10% to 30%. This represents a significant gap between both environments—testing mode versus functional mode—resulting in a less accurate testing due to the fact that the higher switching rate generates more noise on the chip internal power lines during testing.
For instance, for a design with an LBIST scan channel length of 1024, each flip-flop in the LBIST channel has 1024 scan clocks and data shifted 1024 times on each transition. The total number of transitions per channel during the scan phase depends on the current channel content and scanned-in data. Also, during the active clock sequence, as the flip-flop content is more random than during functional usage, more flip-flops will also see a transition and/or “illegal” states will be tested. This larger number of flip-flop toggling leads to a large change in the consumed current per time period and noise across the test circuit that does not represent the real functional usage of the circuit. This results in additional unnecessary guard bending of the circuit that translates directly into an increased voltage/lower frequency sort to overcome the noise resulting in e.g., down-binning to a lower performance sort and/or could result in unnecessary yield loss.